1. Field of the Invention
The present invention relates generally to a system for controlling a microcomputer, and more particularly to such a control system for a microcomputer equipped with a cache.
2. Description of the Prior Art
FIG. 2 is a block diagram showing a general arrangement of a microcomputer. In FIG. 2, numeral 1 represents a microcomputer core for processing data, 2 designates a cache for storing a portion of data of an external storage device in connection with an address for the data, 3 depicts a bus control section for controlling the flow of data between the computer core 1, the cache 2 and an external storage device, 4 denotes an external address bus, 5 indicates an internal address bus, 6 is an external data bus, and 7 designates an internal data bus. Further, numeral 8 represents a microcomputer comprising the microcomputer core 1, the bus control section 3 and the cache 2, and 9 depicts an external storage device for storing data to be processed by the microcomputer core 1.
FIG. 4 is a schematic illustration of a conventional arrangement of a cache (memory). In FIG. 4, numeral 10 represents an input address received from the internal address bus 5, 11 designates a tag address for the input address 10, 12 depicts a set select address for the input address 10, 13 denotes a data memory section for storing the data of the external storage device 9 by 256 sets (address) .times.2 way pages, 14 indicates a tag memory section for storing as the data tag a portion of the addresses on the external storage device 9 for the data to be registered in the data memory section 13 by 256 sets .times.2 ways, 15 indicates a set select decoder section for respectively outputting the tag address and data by 1 set .times.2 ways from the corresponding tag memory section 14 and data memory section 13 on the basis of the set select address 12, and 16 is a 2-way comparator for comparing the tag address of 1 set .times.2 ways outputted from the tag memory section 14 with the tag address 11 of the input address 10 at every way. Further, numeral 17 represents a way selector section for outputting the way data of the data outputted from 2 ways of the data memory section 13 which are verified by the comparator to be in the coincidence states, and 18 designates an output data to be outputted from the cache 2 to the internal data bus 7. Here, the set represents the line address, the way designates the overlapped page of the tag memory 14 or the data memory section 13 where the 0th way indicates the first page and the first way indicates the second page. Accordingly, the capacities of the tag memory 14 and the data memory section 13 are 256.times.2.times.8 bits=32.times.16.times.8 bits and 32.times.16.times.16 bits, respectively.
Each address of 256 sets in the set select decoder section 15 directly corresponds to the set select address 12, and hence each set is expressed by "0000 0000", "0101 1010", for example. The two ways to be selected by the way selector section 17 are respectively expressed by the 0th way and the first way. The data corresponding to the address "0000 0000 0000 0000" is expressed by "(0000 0000 0000 0000)". FIG. 5 is a memory map showing the operation of a conventional cache.
A description will be made hereinbelow with reference to FIGS. 2 and 4 in terms of the data flow in a conventional microcomputer having a cache therein, where for brevity only the instruction for the microcomputer core 1 is considered as the data of the external storage device. The description is first made in terms of the data flow for the FIG. 2 microcomputer 8. The microcomputer core 1 outputs an address to the internal address bus 5 and the instruction data outputted from the cache 2 or the external storage device 9 is supplied through the internal data bus 7 to the microcomputer core 1. When reading out the data from the cache 2, the bus control section 3 sets the external address bus 4 to the high-impedance state. When reading the data from the external storage device 9, the bus control section 3 outputs an address signal to the external address bus 4 so as to read the data from the external data bus 6. This data is given through the internal data bus 7 to the microcomputer core 1 and the registration thereof is made with respect to either of the ways of the cache 2. With a portion of the address 10 to be outputted from the microcomputer core 1 being set as the tag address 11 and the other portion thereof being set as the select address 12, the data of the external storage device 9 to which the microcomputer core 1 accesses is stored in the data memory section 13. Here, the capacity of the external storage device 9 is extremely greater than that of the data memory section 13 of the cache memory 2. The tag address constituting the address of the data stored in the data memory section 13 is stored in the tag memory section 14.
The data flow of the cache will be described hereinbelow with reference to FIG. 4. The input address 10 is received from the microcomputer core 1. The set select address of the input address 10 is given to the set select decoder section 15. The set select decoder section 15 gives set select signals to the ways of the tag memory section 14 and data memory section 13. Each way of the tag memory section 14 supplies a set of tag addresses selected to the comparator 16 corresponding to the way. Each of way of the data memory section 13 outputs a set of data, selected in accordance with the set select signal, to the way selector section 17. The corresponding comparator 16 with a channel performs the comparison between the tag address 11 of the input address 10 and each tag address outputted from each way of the tag memory section 14. The information relating to the way in which the tag addresses are in the coincidence relation to each other is given to the way selector section 17 so that the way selector section 17 outputs the data corresponding to the input address 10. If all the ways are in non-coincident states, the bus control section 3 performs the registration with respect to either of the ways of the data memory section 13.
Secondly, a description will be made hereinbelow with reference to FIGS. 4 and 5 in terms of the registration to the cache 2. For example, in the case that the microcomputer core 1 outputs the addresses from "0000 0000 0000 0000" to "0000 0000 1111 1111" in sequence when the addresses output are not registered in the cache, the tag address "0000 0000" is registered to the tag memory section 14 where the 0th way is the set "0000 0000" and the data "(0000 0000 0000 0000)" is registered to the data memory section 13 where the 0th way is the set "0000 0000", and further the registrations are successively effected to the 0th-way set "0000 0001", 0th-way set "0000 0010". . . 0th-way set "1111 1111". In addition, in the cases where the microcomputer core 1 subsequently outputs the addresses from "0000 0001 0000 0000" to "0000 0001 1111 1111" in sequence, the data are registered into the first-way set "0000 0000" to the first-way set "1111 1111". Moreover, in cases where the microcomputer core 1 continuously outputs the addresses from "0000 0010 0000 0000" to "0000 0010 0111 0111" in sequence, data are newly registered to the 0th-way set "0000 0000" to the 0th-way set "0111 0111" and the previously registered data "(0000 0000 0000 0000)" to "(0000 0000 0111 0111)" are deleted.
Further, a description will be made hereinbelow with reference to FIGS. 4 and 5 in terms of reading-out data from the cache 2. In the case that the microcomputer core 1 repeatedly outputs the addresses from "0000 0010 0000 0000" to "0000 0010 0111 0111" under the condition that the data is registered in the cache 2 as described above, the data registered in the 0th-way set "0000 0000" to the 0th-way set "0111 0111" are outputted from the cache 2 and the external address bus 4 of the microcomputer 8 enters into the high-impedance state. For example, in cases where the microcomputer core 1 outputs "0000 0010 0000 0000", the set "0000 0000" is selected, and the tag address "0000 0010" is outputted from the 0th-way set "0000 0000" of the tag memory section 14 and the tag address "0000 000 1" is outputted from the first-way set "0000 0000" of the tag memory section 14. The tag address of each way is compared with the tag address "0000 0010" of the input address in the comparator 16. Here, since the 0th-way tag address enters into the coincident state, the data "(0000 0010 0000 0000)" of the 0th-way set "0000 0000" is outputted from the way selector section 17.
Since the external address bus 4 has a greater load as compared with the internal address bus 5, the address is arranged to be outputted by the aid of a transistor having a large drive ability. Thus, the amplitude of the current provided to the external bus will vary greatly when a large number of signal lines have to be switched from carrying no current, logic "0", to carrying high current, logic "0". In the case where the address varies from "1111 1111 1111 1111" to "0000 0000 0000 0000" a large variation of current carried by the bus occurs because the current carried in each of the 16 bus lines varies from a high value to a low value thereby causing noise to generate in signal lines coupled to power and ground. Since in the conventional microcomputer 8 having a cache therein the external address bus takes the high-impedance state when the data registered in the cache is read out by the microcomputer core 1, the transistor having a large drive ability does not operate. The conventional cache equally performs the registration with respect to all regions of the external storage device, and hence the addresses to be outputted also become uniform. Accordingly, the large amplitude variation such as variation from "1111 1111 1111 1111" to "0000 0000 0000 0000" and the small amplitude variation such as variation from "0000 0000 0000 0000" to "0000 0000 0000 0001" occur with the same probability. That is, the conventional cache is not equipped with the countermeasures for preventing the noises.